The present invention relates to a method for manufacturing a reservoir capacitor of a semiconductor device.
A semiconductor memory device configured to store data such as program commands includes a Dynamic Random Access Memory (DRAM) and a Static Random Access Memory (SRAM). The DRAM, which enables reading and writing of information, requires a periodic refresh of the stored information or the data will be lost. The DRAM has been widely used as a large-capacity memory in spite of the required refresh operation because of its inexpensive cost per memory cell and improved integration.
Generally, a memory device, that is, a memory cell includes a transistor and a capacitor. The capacitor has a structure where a dielectric material is located between two electrodes. The capacitance of the capacitor is proportional to an electrode surface area and a dielectric constant of a dielectric film, and inversely proportional to a distance between electrodes, that is, the thickness of the dielectric film.
In order to manufacture a capacitor of high capacitance, several methods have been suggested. This includes a method of using a dielectric film having a large dielectric constant, a method of reducing a thickness of a dielectric film, a method of enlarging a surface of a lower electrode, and a method of reducing a distance between electrodes.
However, as the device size of semiconductor memory becomes smaller due to increased integration, it becomes difficult to manufacture a capacitor that can secure sufficient capacitance due to a reduction of the surface area of the electrodes. Also, there is a limit in increasing the dielectric constant without increasing the electrode surface area of the capacitor in order to improve the capacitance of the capacitor. As a result, a concave-type or a cylinder-type capacitor having a three-dimensional structure is developed to increase the electrode surface area without increasing the capacitor foot print.
Several power sources for operating a semiconductor device are required in other regions including a peri region as well as a capacitor of a cell region. When the power sources are supplied, noise is inevitably generated. In order to remove the noise, a reservoir capacitor has been used. The reservoir capacitor is simultaneously formed in other regions including the peri region when the transistor of the cell region is formed. It is preferable to form multiple reservoir capacitors in several regions in the semiconductor device if possible. Generally, the reservoir capacitor uses a MOS capacitor including a gate, a source and a drain.
FIG. 1 is a plane diagram illustrating a conventional method for manufacturing a reservoir capacitor of a semiconductor device.
Referring to FIG. 1, a gate 125 is formed over a semiconductor substrate 100, and an interlayer insulating film (not shown) is formed over the gate 125. After the interlayer insulating film is etched, a conductive material is filled to form a line-structured storage node contact 140. As a result of increasing integration of the semiconductor device, the width of the storage node contact 140 is made continuously smaller. In order to obtain the storage node contact 140, the interlayer insulating film is etched, the conductive material is filled, and an etch-back process is performed on the conductive material. During the process, a portion of the line-structured storage node contact having a narrow width can be disconnected.
FIG. 2 is a cross-sectional diagram illustrating a conventional method for manufacturing a reservoir capacitor of a semiconductor device. FIG. 2 shows a cross-sectional view taken along A-A′.
Referring to FIG. 2, a gate oxide film (not shown), a gate metal layer 110 and a gate hard mask layer 120 are formed over a semiconductor substrate 100, thereby obtaining a gate 125. A first interlayer insulating film 130 is formed over the resulting structure including the gate 125. A photoresist film (not shown) is formed over the first interlayer insulating film 130. An exposing and developing process is performed with a line-structured mask to obtain a photoresist pattern (not shown). The first interlayer insulating film 130 is etched with the photoresist pattern as a mask to obtain a line-structured storage node contact region (not shown). However, when the first interlayer insulating film 130 is etched to form a line-structured storage node contact region, the first interlayer insulating film 130 can be over-etched, thereby etching the lower gate metal layer 110 and create a short circuit (see region “X” of FIG. 2).
After a conductive layer is filled in the line-structured storage node contact region, the conductive layer is etched back to form a line-structured storage node contact 140. When the conductive layer is etched back, a portion of the line-structured storage node contact 140 can be separated, or a gap can be created. (see region “Y” of FIG. 2).
Subsequently, a second interlayer insulating film 150 is formed over the resulting structure including the line-structured storage node contact 140. After a photoresist film is formed over the second interlayer insulating film 150, an exposing and developing process is performed with a hole-structured mask to obtain a photoresist pattern (not shown). The second interlayer insulating film 150 is etched with the photoresist pattern as a mask to form a hole-structured storage node contact region (not shown) over the line-structured storage node contact 140. After a conductive layer is filled in the hole-structured storage node contact region, the conductive layer is etched back to form a hole-structured storage node contact 160.
A lower electrode 170, a dielectric film (not shown) and an upper electrode 180 are formed over the hole-structured storage node contact 160, thereby obtaining a reservoir capacitor.
FIG. 3 is a circuit diagram illustrating a conventional method for manufacturing a reservoir capacitor of a semiconductor device.
Referring to FIG. 3, a region A of FIG. 3 shows when a portion of the line-structured storage node contact 140 is disconnected, and a region B of FIG. 3 shows when the lower gate 125 contacts with the line-structured storage node contact 140 to generate a short.
In FIG. 3, after a gate is formed over a semiconductor substrate, an interlayer insulating film is deposited for forming a line-structured storage node contact. During this process, the interlayer insulating film can be over-etched so that a lower gate metal layer is exposed. In this case, an electric short is generated between the contact and the gate metal layer. Also in FIG. 3, after a conductive layer is filled in the line-structured storage node contact region, the conductive layer is etched back to form a line-structured storage node contact. However, when the line-structured storage node contact is not formed to have a sufficient depth, a portion of the line-structured storage node contact can be separated by the etch-back process.